1. Field of the Invention
This invention relates generally to integrated circuits and, more particularly, to an integrated circuit power supply interconnection technique using a low resistivity substrate and a buried oxide isolation layer.
2. Background Art
Semiconductor integrated circuits include a plurality of transistors, diodes, and the like formed by creating a variety of doped regions in a semiconductor wafer substrate. These regions are formed by performing a number of operations, for example, epitaxial growth, diffusions, ion implantations, etching processes, etc. These operations normally are carried out by a number of masking steps. The devices are then interconnected by a conductive metallization layer to form the desired circuit function.
In prior art structures, it has been conventional for chip power to be distributed by use of two or more metal power busses that lie in close proximity and cross-over signal carrying metal conductors. However, this procedure results in a complex metalization layout due to the number of connections on top of the integrated circuit. Also, as integrated circuits increase in complexity, the amount of metal overlying the regions increases. This increases the capacitance, especially as the operating current requirements increase. Furthermore, each power supply voltage metallization line that crosses over a signal metallization line creates additional capacitance.
These prior art structures comprised a substrate having high resistivity (low doping). However, a high resistivity substrate has a decreased radiation hardness.
Thus, an integrated circuit power supply interconnection technique is needed that decreases the number of metal power busses on top of the chip, reduces capacitance and improves radiation hardness.